1. Field of the Invention
This invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to the fabrication of split-gate flash memory cells.
2. Description of Related Art
A flash memory is one of erasable programmable read-only memories (EPROM) and is also called a non-volatile memory device. Usually, EPROM comprises tow gates, floating gate and control gate. The purpose of a floating gate is to storage charges and the purpose of a control gate is to control data access. The control gate is located above the floating gate and they do not have contact with each other. The floating gate does not connect to any wiring lines but the control gate connects to word lines. The flash memory cell can erase data "block by block", so it can run with higher speed, for example, 1 to 2 seconds.
Recently, a split-gate flash memory has been developed. FIG. 1A through 1D show the manufacturing progression of a split-gate flash memory according to the conventional method. Referring to FIG. 1A, a photoresist layer 11 is formed over a substrate 10 and then a pattern is defined on the photoresist layer 11. Using photoresist layer 11 as a mask, ions, for example, N-type ions, are implanted into the substrate 10 to form source region 12 and drain region 13. Then, the photoresist layer 11 is stripped.
Next, referring to FIG. 1B, a gate oxide layer 14 and a polysilicon layer 16 are formed sequentially over the substrate 10. A pattern is defined on polysilicon layer 16 to form a floating gate 17 as shown in FIG. 1C.
Then, referring to FIG. 1D, a gate oxide layer 18, for example, a silicon dielectric layer, formed by thermal oxidation is formed over floating gate 17. A control gate 19 is formed over gate oxide layer 14 and gate oxide layer 18 by defining a polysilicon layer.
FIG. 2 shows a top view of the forementioned split-gate flash memory. Because source/drain regions are formed before floating gate formation, the alignment accuracy of floating gate to source/drain regions affects the channel length of L1, L2, L1', and L2'. Due to this misalignment, the length of L1 and L1' is not the same and the length of L2 and L2' is not the same. This misalignment results in poor uniformity of cell performance.